Service Chain
• Technology Platform
• Process/PDK
• IP Design/Service/Maturity
• Application Platform
• Design Support
• AE Support for Customer
• Reference Flow
• Tape Out/Assembly/Testing
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• IP Alliance
• EDA Alliance
• Design Service Alliance
• Chip Assembly/Testing
Technical Event
Reference Flows
SMIC provides multiple comprehensive reference flows based on different leading-edge EDA solutions. These reference flows help customers to set up their design environments and drive their designs from RTL to GDSII with simple steps, significantly reducing time-to-production.

These reference flows are jointly developed by SMIC's reference flow team and leading-edge EDA companies including Cadence, Magma, Mentor Graphics, Synopsys and Agilent.

Currently, we offer reference design flow services for logic designs and complex 0.18μm, 0.13μm, 90nm and 65nm SoC designs based on different EDA vendor design environments. Reference design guidelines for the 0.11μm and 55nm half-node processes are also available from SMIC.

For specific information on reference design flows, please select from the menus below.

[SMIC-Cadence Reference Flows]

[SMIC-Synopsys Reference Flows]

[SMIC-Magma Reference Flows]

For more information, please contact your account manager, login to SMIC Now or send us a message.

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